The present invention relates to a dynamic memory circuit composed of insulated gate field effect transistors.
A memory circuit is basically constructed of memory cells as storage units arranged at the intersections of a plurality of word lines arranged in the row direction and a plurality of bit lines (also called as digit lines) arranged in the column direction. Among the plurality of word lines, only one word line is set at a selected level and the memory cells coupled to the selected word line are enabled so as to output data to the bit lines from the enabled memory cells during a read cycle and to take the data of the bit lines into the enabled memory cells in a write or re-written cycle. In the memory circuit thus arranged, if a word line or lines other than the selected one are changed toward the selected level from the non-selected level because of noise or the like, which means that two or more word lines are erroneously selected at the same time, then, two or more memory cells associated to the same bit line are enabled and hence the contents of such enabled memory cells are simultaneously outputted to the same bit line and mixed among them. Thus, the contents of the enabled memory cells are destroyed, resulting in erroneous read or write operations. Particularly when a dynamic type decoder circuits are used to drive the word lines, the above-mentioned problem is markedly observed. Namely, outputs of such dynamic type decoder circuits are placed in a high-impedance state when they are not selected, and hence potential of non-selected word lines coupled to the non-selected decoder circuits are likely to fluctuate due to noise or the like. In more detail, the dynamic type decoder circuit is composed of a NOR gate receiving a plurality of row address signal and a transmission transistor receiving the output of the NOR gate at the gate for transmitting a driving pulse to the word line when the output of the NOR gate is true. For this reason, the non-selected word line is not connected to any of the power supplies to be put in a floating (high-impedance) condition. Consequently, the potential of the non-selected word line readily fluctuates by noise. Under such circumstance, attempts have been made to prevent the non-selected word line from floating by providing a noise prevention circuit to the respective word lines. An example of the noise prevention circuit is such arranged that the non-selected word line is clamped to a reference potential such as a ground potential by inserting a noise prevention transistor between each word line and the reference potential and allowing the noise preventing transistor to conduct during the access period of the memory. However, since the noise prevention transistor connected to the selected word line is also made conducting, the level of the selected word line more or less attenuates. This results in the following problems. Recently, the operating voltage in many such memory circuit has been reduced from 12 V to 5 V. Accordingly, the margin in the operating voltage in each circuit portion of the memory circuit is becoming smaller, making impermissible even the smallest drop in the voltage. With the memory capacity being made greater recently, each memory cell is also being minimized in size, so that the quantity of an electric charge stored therein has been reduced. On the other hand, the parasitic capacity of the bit line is being increased. It has been therefore attempted to completely transmit the electric charge accumulated in the memory cell to the bit line by raising the potential of the selected word line above the supply voltage to drive a transfer transistor of the memory cell in an unsaturated region so as to transfer a small quantity of the charge in the memory cell speedily and effectively. However, because the potential of the selected word line is reduced by the above described noise prevention circuit, the transfer transistor of the memory cell above cannot be driven in the unsaturated region.
For the above reason, an improved noise prevention circuit has been proposed which comprises a first field effect transistor coupled between an associated word line and a reference potential and having a gate connected to a precharge node, a second field effect transistor coupled between the precharge node and the reference potential and having a gate connected to the associated word line, and a third field effect transistor for operatively charging the precharge node during a period of resetting. Operation of the noise prevention circuit structured above is as follows. The precharged node is first charged by the third transistor, and the first transistor is made conductive by the charge at the precharge node when the associated word line is non-selected to keep the associated non-selected word line at the reference potential. However, such a noise prevention circuit must be added to each word line, and each of the improved noise prevention circuit necessitates three transistors. As a result, the pitch at which word lines are arranged is limited to the region where each noise prevention circuit is formed, and cannot be made smaller. This forms an obstacle to the higher integration of a memory circuit.